DATA-2012

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DATA-2011

D3T workshop

November 8-9, 2012

Disneyland Hotel, Anaheim, CA

IEEE International Workshop on Defect and Adaptive Test Analysis (DATA-2012)

Register by Oct. 5 to get the discounted registration rates

Notification of Acceptance: September 15, 2012

Camera Ready Paper: October 15, 2012

Final Presentation Slides: November 2, 2012

DATA-2012 will be held in conjunction with ITC 2012

It just never stops. Every year silicon wafer process technology continues to shrink, more transistors and functions are included into designs, and customers continue to demand even lower dppm. Meanwhile our bosses and managers are always looking at test as an area to reduce product cost, and they expect us to be able to reduce our test costs while also meeting these newer and tougher test challenges and quality goals. So how do we do it?

“How to get more out of test” has led to new methods to learn about defects and IC behavior through the use of innovative analysis techniques. Now questions about how these techniques should be executed and controlled in production, the types and sizes of databases, and even the format and storage of test data itself are becoming critical. Complex problems, such as the control and documentation of dynamic test changes during Adaptive Test, ensuring high quality levels without test escapes, and the practical and realistic limitations of new ideas for board/system testing are all hot industry topics. Closing the knowledge gap about these issues, the processes, the new test techniques, new database requirements, and how defect models and failure data can be used to adapt test flows are the goals of the DATA workshop.

Presentations related to the topics listed below, including papers, case studies, and posters, are being requested for the 2012 workshop on Defect and Adaptive Test Analysis:

Outlier Identification Test Data Analysis Data-Mining Methods for Test Data Processing Data-Driven Testing (DDT) Yield Learning and Analysis Adaptive Test Database requirements High/Low Voltage Testing & Stress Testing Transition and Delay Fault Testing

Reliability and Yield Nanometer Test Challenges Defect Coverage & Metrics Mixed Current/Voltage Testing Economics of Defect Based Testing Fault Localization & Diagnosis Noise and Crosstalk Testing In-System or On-board Testing

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To present at the workshop, send to Arani.Sinha@INTEL.com a PDF version of an extended abstract of at least 1000 words or a full paper (Max 10 pages, double column, 11pt font size, IEEE proceeding format) by August 30, 2012. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on Oct 15, 2012. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome. Ideas or proposals for Embedded Tutorials, Debates, Panel Discussions or “Spot-Light” presentations describing industrial experiences are also invited.

Technical Program Submissions: Arani Sinha Intel, USA. E-mail: Arani.Sinha@INTEL.com

General Information: Jeffrey Roehr Texas Instruments, USA. E-mail: JLRoehr@TI.com