Call for Paper (pdf)

Paper Submission

ITC 2012

Final Program

Organizing/Program Committee



The IEEE International Workshop on

Defect and Adaptive Test Analysis (DATA-2012)


Nov. 8-9, 2012 Disneyland Hotel, Anaheim, CA

Will be held in conjunction with ITC Test Week (ITC-2012)


Previous Events


D3T workshop




Final Program



 Day 1 – Thursday, Nov 8th 


4:00pm – Opening Remarks

Jeff Roehr (Texas Instruments), General Chair DATA-2012

Arani Sinha (Intel), Program Chair DATA-2012


Session 1: DATA 2012 Keynote:

4:15pm – 5:00 pm:

Dan Glotter (CEO, Optimal Test)


Session 2: Adapting to Adaptive Test

5:00pm – 6:30pm

5:00 to 5:30: Adaptive Alternate Analog Test

         Haralampos-G. Stratigopoulos, Salvador Mir (TIMA Laboratory)

5:30 to 6:00: Spatial Correlation Modeling For Probe Test Cost Reduction (Invited talk)

                        Yiorgos Makris (UT Dallas)

6:00 to 6:30: Seven Precautions for Statistical Parametric Test Analysis

          Jeff Tikkanen, Nik Sumikawa, Li-C Wang (UC Santa Barbara), LeRoy Winemberg,

           Magdy S. Abadir (Freescale)

6.30 to 7.00: Chip Level DFT hooks for System Test and Reconfigurability (Invited Talk)

          Sreejit Chakravarty ( LSI Logic)


Workshop Welcome Reception - 7:00pm – 9:00pm


Day 2 – Friday, Nov 9th


Session 3: Embedded Tutorial

8:00 to 9:00: Noise and Variability Challenges in Delay Testing

Adit Singh (Auburn University)



Session 4: A Good Die, or an Outlier: New Ways to Tell

8:00am – 10:30 am

9:00 to 9:30: Mathematical Framework for Selecting Tests for Outlier Detection

                        H.C.M. Bossers, J.L. Hurink, G.J.M. Smit (University of Twente)

9:30 to 10:00: Improving Test Quality Using Data Mining – A Case Study

           Harry H. Chen, Roger Hsu, J.J. Shyr, PaulYoung Yang, ChingCheng Wang (Mediatek)

10:00 to 10:30: Outlier Detection – A Comprehensive Guide to Business & Technical Implementation

             Keith Arnold (Salland Engineering), Peter M. O'Neill (Avago Technologies), Don W.

             Hartman (Test CIM Consulting)


Coffee Break – 10:30AM – 10:50AM


Session 5: The Power Hour

10:50am  – 11:50 am

10:50 to 11:10: Current-Based Dynamic Technique for Accurately Predicting Power-Supply Noise and

                            Path Delay

              Sushmita Kadiyala Rao, Ryan Robucci, Chintan Patel (University of Maryland, Baltimore)

11:10 to 11:30: On the impact of multiple clock domains and intermodulation products on test

                           C. Thibeault, J. Larche (Ecole de technologie superieure, Montreal)

11:30 to 11:50: Test time reduction using Adaptive DFT Methodology for SOCs

                           Darshan Kobla, Sankaran Menon (Intel)



Lunch – 11:50AM – 1:00PM


Session 6:  What do I do with my data?

1:00pm – 2:30pm

1:00 to 1:20: An Extensible Architecture for Transitioning Distributed Test Data to Cloud-Based Analytics

                        Devin Morris, Oscar Rodriguez, Joe Barnhart, Mark Roos (Roos Instruments)

1:20 to 1:40: Post-Silicon Defect Level Estimation from Test Data

                        Kanad Chakraborty (Lattice Semiconductor), Vishwani D. Agrawal (Auburn University)

1:40 to 2:00: Decision Tree Induction from Semiconductor Test Data

                        William Tambellini (Galaxy Semiconductor)

2:00 to 2:20: Test Process Production Triage

          Steve Ledford (Advantest)


Coffee Break – 2:20AM – 2:30PM

Afternoon Coffee sponsored by Galaxy Semiconductor


Session 7: ITRS Roadmap update

2:30 to 3:00: Data Latency issues in ITRS roadmap for Adaptive Test

                        Phil Nigh (IBM)


Session 8:  Panel Discussion: ITRS Adaptive Test Data Flow: Tomorrowland or Fantasyland?

3:00pm – 4:15 pm

Organizers:  Wes Smith (Galaxy Semi), Jennifer Dworak (SMU)