DATA-2013

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DATA-2012

DATA-2011

D3T workshop

IEEE International Workshop on Digital and Analog Test and Data Analysis (DATA-2013)

September 12, 2013

Disneyland Hotel, Anaheim, CA

Submission Deadline: June 28, 2013

Notification of Acceptance: July 22, 2013

Camera Ready Paper (.pdf): August 23, 2013

Final Presentation Slides (.ppt): September 4, 2013

DATA-2013 will be held in conjunction with ITC 2013

Testing of digital logic has made significant improvements in recent years with the use of the stuck-at and delay fault models. Advances in digital test have now led the way to analog and mixed-signal test, looking at analog fault modeling and coverage, testing of very high speed I/O interfaces and protocols, and also issues like power droop and crosstalk in digital logic.

New data mining techniques such as outlier analysis and adaptive test have helped to improve quality by exploiting IC defects that have ‘analog’ signatures, even in digital devices. However, our capability for data analysis, defect modeling, simulation, and fault coverage of analog logic has not kept up with capabilities in the digital domain.

All of this means that many of today’s biggest challenges in test are actually analog challenges, and product and test engineers are trying to discover issues that are often hidden within the volumes of “Big Data” in the TB/Hr to TB/Day range that needs to be processed and efficiently mined.

Besides presentations on "classical" digital product engineering, this year’s workshop is intended to focus on new, novel, and leading edge techniques that are being used for data analysis and the testing of analog issues, either within analog circuits and designs, or for the analog behavior of digital logic. A list of suggested topics for papers and posters to be submitted for this workshop is provided below.

Analog Fault modeling and coverage Analog effects in Digital Logic Embedded Instrumentation (iJTAG) Advanced Product Engineering Techniques Product and Project Case studies Advanced dppm reduction techniques

Adaptive Test for Product Engineers Data Analysis methods Fault Localization and Diagnosis Yield Learning and Analysis I/O Test, Tuning, and Adjustment Analysis of Aging and Reliability

To present at the workshop, send to JLRoehr@TI.com a PDF version of an extended abstract or a full paper (Max 10 pages, double column, 11pt font size, IEEE proceeding format) by June 28. Each submission should include full name and address of each author, affiliation, telephone number, FAX and Email address. Camera-ready papers for inclusion in the digest of papers will be due on Aug 23. Ideas or proposals for Embedded Tutorials, Debates, Panel Discussions and Poster style “Spot-Light” presentations describing industrial experiences or research are also invited.

Technical Program Submissions: Jeffrey Roehr Texas Instruments, USA. E-mail: JLRoehr@TI.com

General Information: Arani Sinha Intel, USA. E-mail: Arani.Sinha@INTEL.com