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IEEE International Workshop on Defects, Adaptive Test, Yield and Data Analysis (DATA-2016)
Nov 17-18 2016
Fort Worth, TX |
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Program |
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Thursday, November 17, 2016 |
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4:00 p.m. - 4:10 p.m. |
Opening Remarks - Arani Sinha (Program Chair) & Jennifer Dworak (General Chair) |
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4:10 p.m. - 5:00 p.m. |
Keynote "Is this the Big Data Inflection Point ?" Bertrand Renaud, CEO of Galaxy Semiconductor and General Manager, Mentor Graphics |
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5:00 p.m. - 6:30 p.m. |
Panel Discussion "Obstacles to Real Time Understanding of Semiconductor Fab and Test Data" Panel Moderator: Anne Meixner, Consultant Participants: |
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John Carulli, Yield Management, Global Foundries Deiter Rather, Data Analytics Vendor, DR Yield Stacy Ajouri, Test Data, Texas Instruments Steve Palosh, EDA Yield Tools, Synopsys Jason Rivers, Design-DFM, AMD |
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6:30 p.m. - 7:00 p.m. |
Table top demonstrations Mentor Graphics, Optimal Plus, Qualtera |
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7:00 p.m. - 9:00 p.m. |
Reception |
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Friday, November 18, 2016 |
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8:00 a.m. - 10:00 a.m. |
Big Data and Test: What do the Experts think ? |
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8:00 a.m. - 8:40 a.m. |
Invited Talk: "Using OEE Data to Drive Manufacturing Excellence at Test" Dale Ohmart, Texas Instruments |
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8:40 a.m. - 9:20 a.m. |
Invited Talk: "Real-Time Big Data Collection and Analytics for Enhancing Quality, Yield and Manufacturing Control" Paul Simon and Thomas Harper, Qualtera |
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9:20 a.m. - 10:00 a.m. |
Invited Talk: "Cognitive Computing and Test" Anne Gattiker, IBM |
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10:00 a.m. - 10:30 a.m. |
Break |
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10:30 a.m. - Noon |
Technical Paper Session 1: • "Accelerating Characterization with Real Time & Offline Shmoo Type Analysis Using SEMI TEMS - based Data Streaming and Advanced Data Mining" Marc Hutner, Keith Thomas (Teradyne Inc.) Steve McDowall, Wes Smith (Galaxy Semiconductor) • "Novel Use of Design Data During In-Line Inspection for Early Identification of Scan Chain Failures" Pierre-Jerome Goirand, Laurent Tetar, Nelly Feldman (STMicroelectronics) Narayani Narasimhan, Sergei Bakarian, Jim Young, Mike vonDenHoff, Sagar A. Kekare (KLA-Tencor) • "Combining Principal Component Analysis with PAT for Identification of Discrepant Material" David Kantorovich, Ahmet Kaya and Dan Sebban (Optimal Plus) |
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Noon - 1:00 p.m. |
Lunch |
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1:00 p.m. - 2:30 p.m. |
Technical Paper Session 2: • "Improved Understanding of IP Manufacturability—A Proposal to Share Data between Fab, Test and Design" Anne Meixner, Consultant • "A New Yield Learning Analysis Approach for Fabless Organizations" Geoffrey P. O'Donoghue, Dirk Niggemeyer, Integrated Yield Solutions • "Using Big Data and Machine Learning to Support Defective Parts Investigation in IC's Manufacturing" Susan Aguilar, Rahima Mohammed, Rafael Monge, Intel Corporation |
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2:30 p.m. - 2:50 p.m. |
Break |
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2:50 p.m. - 4:10 p.m. |
Technical Presentations 3: • "Test Time Reduction Using Outlier Screening" Amit Nahar, Texas Instruments • "Towards Autonomous Analytics - From Learning Data to Learning Analyst's Intent" Sebastian Siatkowski and Li-C. Wang, UC Santa Barbara • "Detecting a Trojan Die in 3D Stacked Integrated Circuits" Soha Alhelaly and Jennifer Dworak (SMU) Al Crouch (SiliconAid Solutions) • "Bench-top environment for accelerated bring-up of ATPG patterns" Pavan G, Aditya Joshi, Venkata Rangam Totakura (Cypress Semiconductor) Pawan Kumar Rukmangada, Thryambak Chandilya, Geir Eide (Mentor Graphics) |
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